1. Technical Field
The invention relates to chemical-mechanical planarization. More particularly, the invention relates to a chemical-mechanical planarization controller.
2. Description of the Prior Art
Chemical-Mechanical Planarization (CMP) is an important step in the processing of semiconductor wafers and is playing an increasingly critical role in semiconductor microelectronics fabrication (see The National Technology Roadmap for Semiconductors, Semiconductor Industry Association, San Jose, Calif. 1997; J. M. Steigerwald, S. P. Murarka, R. J. Gutman, Chemical Mechanical Planarization of Microelectronic Materials, Wiley Interscience, 1997; and W. J. Patrick, W. L. Guthrie, C. L. Stanley, and P. M. Schiable, Application of Chemical Mechanical Polishing to the Fabrication of VLSI Circuit Interconnection, J. Electrochem. Soc., 138, 1778–1784, 1991).
CMP is a process for material removal that uses chemical and mechanical actions to produce a planar mirror-like wafer surface for subsequent processing. For a nominally uniform wafer, CMP is capable of producing an atomically-smooth and damage-free surface at feature level, which is a basic requirement for semiconductor fabrication below 0.25μ (see The National Technology Roadmap for Semiconductors, Semiconductor Industry Association, San Jose, Calif. 1997). The superiority of CMP over traditional etchback techniques with respect to defect reduction and yield enhancement has been demonstrated (for application to tungsten, see K. Wijekoon et al., Tungsten CMP Process Developed, Solid State Technology, April 1998). CMP also has fewer processing steps as compared to traditional etchback methods. CMP is also an enabling technology for transition to copper interconnects. Optimal CMP maximizes planarity and minimizes oxide erosion and dishing.
Integrated Circuit (IC) makers continue to adopt CMP for advanced manufacturing, and CMP has now joined standard processing techniques, such as deposition, etch, and lithography in strategic importance. State-of-the-art Application-Specific Integrated Circuits (ASIC) chips, and advanced Dynamic Random Access Memories (DRAMs) are among the latest applications where CMP is being used. Planarization of features on a semiconductor wafer is a critical factor in Ultra Large-Scale Integration (ULSI) processing (0.25μ) for fabrication of multi-levels of wiring and for trench isolation. As device geometries shrink, there are increasingly more stringent requirements on deposition, etch, and lithography due to increases in aspect ratio of device structures. There is a lithography constraint on the step height, i.e. feature variations that require the pattern entirely be confined to within a depth of focus of ±0.3μ. For DRAM applications, planarization processes for trench isolation require thickness to be controlled within ±0.1μ or better. This requirement when achieved over all features is referred to as global planarization. For integrating CMOS technologies of a quarter micron (0.25μ or below), CMP is being used in advanced applications such as Shallow Trench Isolation (STI).
Description of the CMP Process
One distinguishes different kinds of CMP systems by its kinematic motions, e.g. rotational, orbital or linear CMP systems. A schematic of a typical rotational CMP machine is shown in FIG. 1 (see, e.g. J. M. Steigerwald, S. P. Murarka, R. J. Gutmann, Chemical Mechanical Planarization of Microelectronic Materials, Wiley Interscience, 1997). The rotating wafer 10 borne by a wafer carrier 11 rests on a rotating pad system 12, consisting of one or more pads. The pad system is part of a polishing table 13. A pressurized retaining ring surrounds the wafer and holds it in place. A nominally uniform load pressure distribution acts on the wafer. For oxide or silicon polishing, an alkaline slurry 14 of colloidal silica is continuously fed to the wafer/pad interface. Although the detailed mechanisms are under investigation, a surface layer forms as a result of chemical processes, and the resulting reaction product is removed by the mechanical abrasive action of the pad and the slurry. The behavior is most complex at the edge of the wafer. The differential velocity and pressures, as well as slurry composition, determine the local removal rate. The dynamic nature of the deformation of the pad determines the local pressure gradients across the wafer and the resulting planarization uniformity. To planarize features across the whole wafer evenly, the material removal rate across the wafer must be uniform.
State-of-the-Art CMP Process Control
The goal of CMP processing is to achieve a specified thickness and uniformity in a repeatable fashion. Major problems in CMP include controlling the material removal or, equivalently, the material removal rate, and the uniformity on each run, and reproducibility from run-to-run. Typically an in-situ sensor is used to detect the end-point of the process, i.e. to detect when the desired amount of material is removed, at which point in time the process is stopped.
A widely used approach for controlling CMP performance involves the following two-step trial-and-error process (see, e.g., R. Allen, C. Chen, K. Lehman, R. Shinagawa, V. Bhaskaran, CMP: Where Does It End, Yield Management Solutions Magazine, Vol. 4, No. 1, 2002):    (1) process parameters are adjusted to give good uniformity, and    (2) end-point control using an in-situ rate sensor is used to achieve desired material removal thickness.
From a control theory perspective, this approach is called Open-loop control, because the control variables are not adjusted during the run. Neither are these control variables tuned from run to run, but held constant. This approach has at least the following limitations:
First, the process operating window is very narrow, because the process is finely tuned to generate a recipe where the input process parameter values yield acceptable uniformity for most materials. Therefore, the process performance is not robust, being very sensitive to disturbances and input variations, such as pad wear, temperature variations, slurry concentration, sensor drift, etc. Furthermore this approach does not work well for different materials.
Second, if the output specifications for the planarization are changed, then considerable trial-and-error is required to re-establish the input operating conditions necessary to obtain uniformity. These limitations require intensive process monitoring as well as the availability of many (expensive) test wafers.
One approach that addresses some of these limitations is called Run-to-run control. In run-to-run control, the control variables are held constant during the run, but may be modified between runs based on in-line and/or ex-situ (post-process) measurements. This approach works well for compensating slow drifts such as pad wear or slow temperature variations, but does not work for wafer-to-wafer variations such as variations in incoming thickness profile, variations in slurry concentrations, etc.
It would be advantageous to provide an approach that addresses all of these limitations.